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Design and Test Technology for Dependable Systems-on-Chip

Design and Test Technology for Dependable Systems-on-Chip

Copyright: © 2011 |Pages: 578
ISBN13: 9781609602123|ISBN10: 1609602129|EISBN13: 9781609602147
DOI: 10.4018/978-1-60960-212-3
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MLA

Ubar, Raimund, et al., editors. Design and Test Technology for Dependable Systems-on-Chip. IGI Global, 2011. https://doi.org/10.4018/978-1-60960-212-3

APA

Ubar, R., Raik, J., & Vierhaus, H. T. (Eds.). (2011). Design and Test Technology for Dependable Systems-on-Chip. IGI Global. https://doi.org/10.4018/978-1-60960-212-3

Chicago

Ubar, Raimund, Jaan Raik, and Heinrich Theodor Vierhaus, eds. Design and Test Technology for Dependable Systems-on-Chip. Hershey, PA: IGI Global, 2011. https://doi.org/10.4018/978-1-60960-212-3

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Designing reliable and dependable embedded systems has become increasingly important as the failure of these systems in an automotive, aerospace or nuclear application can have serious consequences.

Design and Test Technology for Dependable Systems-on-Chip covers aspects of system design and efficient modelling, and also introduces various fault models and fault mechanisms associated with digital circuits integrated into System on Chip (SoC), Multi-Processor System-on Chip (MPSoC) or Network on Chip (NoC). This book provides insight into refined “classical” design and test topics and solutions for IC test technology and fault-tolerant systems.

Table of Contents

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Front Materials
Title Page
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Copyright Page
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Book Series
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Editorial Advisory Board
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Foreword
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Preface
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Chapters
Chapter 1
Zebo Peng
Design, Modeling and Verification
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Chapter 2
Heinrich Theodor Vierhaus
Faults, Compensation and Repair
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Chapter 3
Raimund Ubar
Fault Simulation and Fault Injection
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Chapter 4
Matteo Sonza Reorda
Test Technology for Systems-on-Chip
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Chapter 5
Erik Larsson
Test Planning, Compression and Compaction in SoCs
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Back Materials
Compilation of References
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About the Contributors
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Index
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