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FPGA Memory Optimization in High-Level Synthesis

FPGA Memory Optimization in High-Level Synthesis

Mingjie Lin, Juan Escobedo
Copyright: © 2020 |Pages: 31
ISBN13: 9781522598060|ISBN10: 1522598065|ISBN13 Softcover: 9781522598077|EISBN13: 9781522598084
DOI: 10.4018/978-1-5225-9806-0.ch003
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MLA

Lin, Mingjie, and Juan Escobedo. "FPGA Memory Optimization in High-Level Synthesis." FPGA Algorithms and Applications for the Internet of Things, edited by Preeti Sharma and Rajit Nair, IGI Global, 2020, pp. 51-81. https://doi.org/10.4018/978-1-5225-9806-0.ch003

APA

Lin, M. & Escobedo, J. (2020). FPGA Memory Optimization in High-Level Synthesis. In P. Sharma & R. Nair (Eds.), FPGA Algorithms and Applications for the Internet of Things (pp. 51-81). IGI Global. https://doi.org/10.4018/978-1-5225-9806-0.ch003

Chicago

Lin, Mingjie, and Juan Escobedo. "FPGA Memory Optimization in High-Level Synthesis." In FPGA Algorithms and Applications for the Internet of Things, edited by Preeti Sharma and Rajit Nair, 51-81. Hershey, PA: IGI Global, 2020. https://doi.org/10.4018/978-1-5225-9806-0.ch003

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Abstract

High-level synthesis (HLS) with FPGA can achieve significant performance improvements through effective memory partitioning and meticulous data reuse. In this chapter, the authors will first explore techniques that have been adopted directly from systems that possess a fixed memory subsystem such as CPUs and GPUs (Section 2). Section 3 will focus on techniques that have been developed specifically for reconfigurable architectures which generate custom memory subsystems to take advantage of the peculiarities of a family of affine code called stencil code. The authors will focus on techniques that exploit memory banking to allow for parallel, conflict-free memory accesses in Section 3.1 and techniques that generate an optimal memory micro-architecture for data reuse in Section 3.2. Finally, Section 4 will explore the technique handling code still belonging to the affine family but the relative distance between the addresses.